From sand to silicon. From physics to geopolitics. A first-principles map of the most strategically important industry on the planet — its players, layers, chokepoints, and the myths that distort public understanding.
Before understanding the industry, you need to understand the language. These terms are used constantly but rarely explained correctly — or honestly.
The process of projecting a circuit pattern (called a "mask") onto a silicon wafer coated in light-sensitive material. The light hardens the coating, and everything else is chemically etched away — leaving the circuit. The finer the light's wavelength, the smaller the features you can draw.
Originally referred to the physical size of a transistor gate (in nanometers). Past ~65nm, it became a marketing name. Intel's "10nm" and TSMC's "7nm" had similar transistor density. The number signals a generation of process technology, not a literal physical dimension. Never compare nm numbers across fabs.
DUV (Deep Ultra Violet) uses 193nm wavelength light — adequate for nodes to ~7nm with multiple patterning passes. EUV (Extreme Ultra Violet) uses 13.5nm wavelength — 14× shorter — enabling single-pass patterning of sub-7nm features. EUV machines cost ~$200M each and only ASML makes them.
A Fab is a chip manufacturing facility. A Fabless company (Apple, NVIDIA, Qualcomm) designs chips but outsources all manufacturing. A Foundry (TSMC) manufactures for others without designing its own chips. An IDM (Intel, Samsung) does both.
A thin circular disc of ultra-pure silicon on which hundreds or thousands of chips are simultaneously patterned. Standard sizes: 200mm (8 inch) and 300mm (12 inch). Larger wafers = more chips per batch = lower cost per chip. Requires 9N purity — 99.9999999% pure silicon.
The percentage of chips on a wafer that actually work correctly after manufacturing. A fab running 95% yield is excellent; 50% is catastrophic. Yield is the hidden competitive weapon — TSMC's yield superiority over Samsung is arguably as important as their node lead. Low yield = most of an expensive wafer is scrapped.
FinFET adds a vertical "fin" to the transistor, giving the gate three-sided control — sharply reducing leakage. GAAFET (Gate-All-Around) wraps the gate entirely around the channel — even better control. Used at Samsung 3nm and TSMC N2. Each step enables smaller, more power-efficient transistors.
At extremely small scales, electrons can probabilistically "tunnel" through a barrier that should block them — like the gate oxide. This causes leakage current even when a transistor is "off." Solved by High-K Metal Gate (HKMG) dielectrics and FinFET/GAAFET architectures — not by slowing node shrinks.
Electronic Design Automation — software that makes chip design possible. Without EDA tools (Synopsys, Cadence), you cannot design a modern chip, period. These tools simulate, place, route, and verify that billions of transistors will actually function before a dollar is spent on manufacturing.
Instead of one massive chip, chiplets break designs into smaller specialized dies packaged together. AMD's Ryzen: CPU cores on one die, I/O on another. NVIDIA's H100 stacks HBM memory via CoWoS. Better yield, mix-and-match nodes, lower cost. The new performance frontier as EUV scaling slows.
A material innovation replacing SiO₂ gate oxide with hafnium-based dielectrics. Physically thicker (reducing quantum tunneling) while electrically equivalent to a much thinner SiO₂ layer. Intel introduced HKMG in 2007. It was the primary fix for tunneling leakage that would otherwise have halted transistor scaling entirely.
A chemical coating applied to wafers that reacts to light during lithography. Exposed areas harden or soften; the rest is washed away — transferring the circuit pattern. EUV requires specially formulated chemically amplified resists. Japan's JSR and Shin-Etsu supply ~90% of the world's photoresist — a silent but razor-sharp chokepoint.
The semiconductor supply chain is the most geographically dispersed, technically specialized, and strategically fragile industrial system humanity has ever built. No single country controls all layers.
No single country controls the entire stack. Semiconductor power is distributed across nations — which creates both resilience and fragility depending on the layer in question.
The strategic materials in semiconductors are less about geological "rarity" and more about concentrated processing capability. Silicon is the second most abundant element on Earth — its scarcity is in purification, not supply.
Popular and social media perpetuate deeply misleading narratives about semiconductors. Each one warps public and policy understanding in ways that have real consequences.
"The smaller the nm number, the faster and better the chip." A 3nm chip is always superior to a 28nm chip.
The nm number is a marketing label past 65nm, not a physical measurement. A 28nm chip is often optimal for automotive MCUs, analog, RF, and power ICs. Performance depends on architecture, memory bandwidth, packaging, and workload — not node name.
"EUV chips run hotter because of the extreme ultraviolet radiation used to make them."
EUV is a manufacturing process. The finished chip contains no UV radiation. Advanced node chips run cooler per computation — lower voltage, fewer transistor switches per task. The MacBook Air's fanless design exists because of EUV efficiency, not despite it.
"China is ahead in chips because it manufactures so many electronics products."
China assembles electronics — a very different thing from semiconductor manufacturing. China cannot currently make chips below ~7nm equivalent without EUV access. ASML has even been blocked from servicing China's existing DUV machines.
"India got old, inferior technology from the Tata-ASML deal."
28nm–110nm covers ~60–70% of global chip volume by units. It's the right entry point for automotive, industrial, and defence markets. China would consider this deal an upgrade — it is being denied even DUV servicing. India's challenge is execution, not technology tier.
"Semiconductor scarcity is fundamentally about rare earth elements and geological availability."
Silicon is the second most abundant element on Earth. Scarcity is in purification, process chemistry, and equipment capability — not geology. The most dangerous chokepoints are neon gas, photoresists, and gallium processing — concentration of expertise, not of atoms.
"Any country can build a chip fab by buying the equipment and hiring engineers."
A fab is not the equipment — it's process knowledge encoded in millions of recipe parameters built over decades. TSMC's advantage isn't the ASML machines (Samsung has them too). It's yield know-how that cannot be bought, copied, or reverse-engineered on any reasonable timescale.
Since 2019, semiconductors have become the primary battlefield of great power competition. The weapons are export controls, equipment restrictions, and supply chain reorganization — not military force.
India is entering the semiconductor stack not at the top, but at the right point — leveraging its design talent, growing domestic market, and strategic positioning as a US-aligned alternative to China.
A rapid-fire reference for the terms that appear constantly in semiconductor coverage, explained plainly.